Analog Delay Lock Loops (DLL's) are commonly used in modern integrated circuits (IC's) to synthesize clock phases. FIG. 1 schematically illustrates a basic structure of a conventional analog DLL 10. The analog DLL 10 includes a phase detector (PD) 12, a charge pump circuit (CP) 14, a loop filter capacitor (C) 16, and a voltage-controlled-delay (VCD) 18. The DLL 10 locks the delay of the VCD to one reference cycle. The VCD output is typically a delayed clock signal (Clk). Thus, a rising edge of the delayed clock (Clk) is aligned with the next rising edge of the reference clock signal (Ref) in an ideal DLL. In an actual DLL, however, phase alignment between the delayed clock and the reference signal is subject to miscellaneous noises and other non-idealities.
The DLL performance is typically characterized by the statistical distribution of the delayed clock timing with respect to the reference signal. The spread of the distribution (measured in pico second) is referred to as jitter, and the mean of the distribution is referred to as static phase offset (SPO). Both jitter and SPO are key performance parameters of a DLL. Jitter is contributed by many noises and interference sources of the DLL, while static phase offset is contributed by the fixed asymmetry or mismatch in the phase detector and the charge pump circuit. The static phase offset of a DLL is revealed on the combined transfer curve of its phase detector and charge pump circuit. FIG. 2 schematically illustrates the time-averaged charge pump output current (Icp) as a function of the phase error seen by the phase detector. For an ideal DLL, the curve should pass through the origin as indicated by a broken line. That is, when the time-averaged output current of the charge pump circuit diminishes to zero in the lock-state, the phase error is also zero. However, as shown in FIG. 2, the actual curve 20 is shifted by the amount of the static phase offset (SPO).
As shown in FIG. 1, the charge pump circuit 14 includes two current sources 22 and 24, a first active device (M1) 26, and a second active device (M2) 28. The voltage of the loop filter capacitor 16 should be a constant in the steady state, and the mismatch between a pump-up current (Iu) and a pump-down current (Id) is one of the SPO sources. This means that the total electric charge supplied through the first active device 26 must be canceling out with the total electric charge supplied through the second active device 28 each cycle. Since the first active device 26 is controlled by a first signal (Upb) and the second active device 28 is controlled by a second signal (Dn), the electric charges through the first active device 26 each cycle is the pulse-width (Wu) of the first signal Ubp times the pump-up current (i.e, Wu×Iu), and that of the second active device 28 is the pulse-width (Wd) of the second signal Dn times the pump-down current (i.e., Wd×Id). Thus, the mismatch between the pump-up and -down currents Iu and Id (i.e., a non-zero SPO) leads to a pulse-width difference between the first and second signals Upb and Dn.
Another SPO source comes from the opposite polarities of the signals Upb and Dn. The phase detector 12 is designed to be completely symmetrical from its two inputs up to the internal signals Up and Dn. In other words, the circuit that sets the pulse width of the signal Up in accordance with the reference signal (Ref) is identical to the circuit that sets the pulse width of the signal Dn in accordance with the delayed signal (Clk). The charge pump circuit 14, however, is not symmetrical since the pump-up switch M1 (first active device 26) is a PMOS requiring a “low” to turn on, while the pump-down switch M2 (second active device 28) is a NMOS requiring a “high” to turn on. Thus, the signal Up in the phase detector 12 needs to be inverted (to be the signal Upb) to control the first active device 26. This polarity inversion breaks the circuit symmetry and therefore causes the SPO.
In addition, since the first and second active devices 26 and 28 are of the opposite types and different sizes, their gate-to-drain feed-through currents are also different when switching. Similarly to the up-down current mismatch (Iu-Id mismatch) mentioned above, the clock-feed-through (CFT) mismatch between the active devices 26 and 28 also contributes to the SPO. The static phase offsets due to the Iu-Id mismatch and the polarity inversion are referred to as the systematic SPO or circuit SPO. The systematic SPO can be traced back to the lack of schematic-level symmetry between the pump-up side and the pump-down side of the DLL. In addition to systematic SPO, there are also random SPO or process SPO, which are due to random variations of device parameters, such as threshold voltage, channel length, and the like, in the phase detector and the charge pump circuit.
One of the pump-up and pump-down currents is current-mirrored from the other to ensure that they will track over variations of process, voltage, and temperature (PVT). Since the mirroring accuracy directly affects the SPO, cascode techniques are commonly used to meet accuracy demands. FIG. 3 schematically illustrates a conventional charge pump circuit 30 using the cascode techniques. The charge pump circuit 30 includes cascode current sources 32 and 34 (devices M5, M7 and M6, M8). Active devices 31 and 33 (M3 and M4) and an operational amplifier 35 (OP1) form a current dumping path that keep the current flowing (through active devices M5–M8) during the time period when the active devices 36 and 37 (M1 and M2) are turned off. However, such cascode mirroring increases the voltage headroom requirements of the current sources. This is undesirable because the voltage range at the charge pump output determines the tuning range of the VCD and thus the working frequency range of the DLL. Particularly for DLL's using low power supply voltages, the Iu-Id matching often needs be done without sacrificing the CP output range.
FIG. 4 schematically illustrates a mirroring scheme 40 suitable for low voltage environments. An operational amplifier OP2 and a DC replica circuit (M9–M12) of the charge pump circuit adjust the pump-up current Iu to match with the pump-down current Id. Nodes 42 and 44 are virtually shorted by the operational amplifier 41 (OP2), since the nodes 42 and 44 are connected to the two inputs of the operational amplifier 41. Since all matching devices see the matched Vds bias on them, it has a mirroring accuracy comparable to that of a cascode design.
As shown in FIG. 4, the mirroring circuit 40 includes compensating capacitors 43 and 45 (M7 and M8). The impact of the clock-feed-through mismatch to the SPO is usually mitigated using the compensating capacitors 43 and 45 by introducing an opposite clock-feed-through current. The opposite current at least partially cancels with the original clock-feed-through current in the active devices 46 and 46 (M1 and M2). The capacitor sizes are determined through circuit simulations, and thus overall effectiveness of the cancellation is subject to the accuracy of the device models used in simulations. In this approach, the capacitor sizes can be optimized only for a given process-voltage-temperature case at a given clock frequency, and thus the current cancellation using the compensating capacitors is limited. Furthermore, any of the conventional approaches of DLL designs does not provide a satisfactory solution to the SPO due to the polarity inversion.